Proceedings of the 8th Great Lakes Symposium on VLSI

Proceedings of the 8th Great Lakes Symposium on VLSI

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Figure 5: Block-diagram of the built-in test macromodel. ... X0.9 X0.1 Aagt;B? Aagt;B? prop D-GI \ xo.s Aagt;B7 f3agt;4E Deny B Aagt;Bagt;C? C MM B Aagt;Bagt;C? C Reference voltegea , The main limitations of the test circuit are the delays to be measured. ... Theory and Applications (JETTA), 6 (3), June 1995, pp. ... March 17-20 1997, pp.


Title:Proceedings of the 8th Great Lakes Symposium on VLSI
Author: Magdy A. Bayoumi, Graham Jullien
Publisher: - 1998
ISBN-13:

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